1. Field of the Invention
The present invention pertains to non-volatile memory cells (e.g., non-volatile memory cells that include at least one MOS transistor) and to methods of programming, erasing, and reading them.
2. Description of the Related Art
The expression “PMOS transistor” herein denotes a P-channel MOSFET device. The expression “NMOS transistor” herein denotes an N-channel MOSFET device.
The term “N-well” herein denotes a well of N-type semiconductor material. The term “P-well” herein denotes a well of P-type semiconductor material.
One type of conventional non-volatile memory cell is described in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987. This cell includes a single MOS transistor having a stacked gate structure. The stacked gate structure includes a control gate, a floating gate, a dielectric layer insulating the control gate from the floating gate, and additional dielectric material (gate oxide) insulating the floating gate from the transistor body. The cell is programmed by biasing the control gate, source, and drain to produce hot electrons in the body and accelerate the hot electrons across the gate oxide into the floating gate. The charge accumulated on the floating gate during programming is stored there until the cell is erased. The programmed cell is erased by biasing the control gate, source, and drain to cause electrons to move (via Fowler-Nordheim tunneling) from the floating gate to the source or drain. As an example, an implementation of the cell that includes an NMOS transistor can be programmed by holding the transistor's drain at a high potential relative to the source, and briefly holding the control gate at an even higher potential relative to the source to produce hot electrons in the body and accelerate the hot electrons across the gate oxide into the floating gate. The electrons stored in the floating gate during the programming operation increase the transistor's threshold voltage. During a readout operation, the control gate, source, and drain are biased in such a manner that significant current flows through the NMOS transistor's channel if the transistor is not programmed (or has been programmed and then erased) but no significant current flows through the transistor's channel if the transistor is programmed. Thus, the amount of channel current sensed during the readout operation indicates whether the cell is or is not programmed.
Another type of conventional non-volatile memory cell is described in U.S. Pat. No. 6,137,723, issued Oct. 24, 2000. This cell includes a transistor having a source and drain formed in a well, and a floating gate separated from the well by insulating material (gate oxide). The cell is programmed by biasing the source, drain, and well to induce avalanche breakdown, thereby producing substrate hot electrons which accelerate across the gate oxide into the floating gate. The charge accumulated on the floating gate during programming is stored there until the cell is erased. The programmed cell is erased by irradiation (using ultraviolet radiation). An implementation of the cell that includes a PMOS transistor can be programmed by grounding the well, holding the transistor's drain at a large negative potential, and either floating or grounding the source. The cell can be read by grounding the well and source, applying a read voltage to the drain, and determining whether channel current does or does not flow from the drain to the source in response to such biasing of the cell.
Another type of conventional non-volatile memory cell is described in U.S. Patent Application Publication Number US 2004/0080982, published on Apr. 29, 2004. This cell includes a PMOS transistor and an NMOS transistor whose drains are coupled together by a metal structure. The transistors share a control gate and also share a floating gate. The floating gate is insulated from the control gate and from the bodies of the transistors. The cell is programmed by biasing the sources, drains, and control gate to cause electrons (produced by band-to-band tunneling) to be injected to the floating gate. However, due to the structure of the cell of U.S. Publication No. US 2004/0080982, which requires that one transistor is implemented in N-type semiconductor material (e.g., in an N-well) and the other in P-type semiconductor material (e.g., in a P-well) with field oxide isolating one transistor from the other, an array of such cells cannot be implemented with sufficient density for many applications.
There is a need for a non-volatile memory cell that can be efficiently and rapidly programmed and erased (without drawing significant current), and can be implemented compactly so that an array of the cells can be implemented with high density (many cells per unit area).